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<a href="core__cm0plus_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">/**************************************************************************/</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * Copyright (c) 2009-2018 Arm Limited. All rights reserved.</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * SPDX-License-Identifier: Apache-2.0</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * Licensed under the Apache License, Version 2.0 (the License); you may</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * not use this file except in compliance with the License.</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * You may obtain a copy of the License at</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * www.apache.org/licenses/LICENSE-2.0</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * Unless required by applicable law or agreed to in writing, software</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * distributed under the License is distributed on an AS IS BASIS, WITHOUT</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * See the License for the specific language governing permissions and</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * limitations under the License.</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> */</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;</div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="preprocessor">#if   defined ( __ICCARM__ )</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="preprocessor">  #pragma system_include         </span><span class="comment">/* treat file as system include file for MISRA check */</span><span class="preprocessor"></span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="preprocessor">#elif defined (__clang__)</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="preprocessor">  #pragma clang system_header   </span><span class="comment">/* treat file as system include file */</span><span class="preprocessor"></span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;</div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="preprocessor">#ifndef __CORE_CM0PLUS_H_GENERIC</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="preprocessor">#define __CORE_CM0PLUS_H_GENERIC</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;</div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;</div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160; <span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="comment"> *                 CMSIS definitions</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment"> ******************************************************************************/</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="cmsis__version_8h.html">cmsis_version.h</a>&quot;</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160; </div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="comment">/*  CMSIS CM0+ definitions */</span></div><div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#a31329dc8c47fc34ca3cacbfd4c66a19a">   66</a></span>&#160;<span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  </span></div><div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#a70604168ca42eff80802c151188a59d1">   67</a></span>&#160;<span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   </span></div><div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#afbc98e5d6904c90236f737adb89af711">   68</a></span>&#160;<span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN &lt;&lt; 16U) | \</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">                                       __CM0PLUS_CMSIS_VERSION_SUB           )  </span></div><div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#a63ea62503c88acab19fcf3d5743009e3">   71</a></span>&#160;<span class="preprocessor">#define __CORTEX_M                   (0U)                                       </span></div><div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#aa167d0f532a7c2b2e3a6395db2fa0776">   76</a></span>&#160;<span class="preprocessor">#define __FPU_USED       0U</span></div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;</div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;<span class="preprocessor">#if defined ( __CC_ARM )</span></div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;<span class="preprocessor">  #if defined __TARGET_FPU_VFP</span></div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;<span class="preprocessor">#elif defined (__ARMCC_VERSION) &amp;&amp; (__ARMCC_VERSION &gt;= 6010050)</span></div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;<span class="preprocessor">  #if defined __ARM_PCS_VFP</span></div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;<span class="preprocessor">#elif defined ( __GNUC__ )</span></div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;<span class="preprocessor">  #if defined (__VFP_FP__) &amp;&amp; !defined(__SOFTFP__)</span></div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;</div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;<span class="preprocessor">#elif defined ( __ICCARM__ )</span></div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;<span class="preprocessor">  #if defined __ARMVFP__</span></div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;<span class="preprocessor">#elif defined ( __TI_ARM__ )</span></div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;<span class="preprocessor">  #if defined __TI_VFP_SUPPORT__</span></div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;</div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;<span class="preprocessor">#elif defined ( __TASKING__ )</span></div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;<span class="preprocessor">  #if defined __FPU_VFP__</span></div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;<span class="preprocessor">#elif defined ( __CSMC__ )</span></div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;<span class="preprocessor">  #if ( __CSMC__ &amp; 0x400U)</span></div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;<span class="preprocessor">    #error &quot;Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)&quot;</span></div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;</div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;</div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;<span class="preprocessor">#include &quot;<a class="code" href="cmsis__compiler_8h.html">cmsis_compiler.h</a>&quot;</span>               <span class="comment">/* CMSIS compiler specific defines */</span></div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;}</div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;</div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM0PLUS_H_GENERIC */</span><span class="preprocessor"></span></div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;</div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;<span class="preprocessor">#ifndef __CMSIS_GENERIC</span></div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;</div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;<span class="preprocessor">#ifndef __CORE_CM0PLUS_H_DEPENDANT</span></div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;<span class="preprocessor">#define __CORE_CM0PLUS_H_DEPENDANT</span></div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;</div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160; <span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;</div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;<span class="comment">/* check device defines and use defaults */</span></div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;<span class="preprocessor">#if defined __CHECK_DEVICE_DEFINES</span></div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;<span class="preprocessor">  #ifndef __CM0PLUS_REV</span></div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;<span class="preprocessor">    #define __CM0PLUS_REV             0x0000U</span></div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;<span class="preprocessor">    #warning &quot;__CM0PLUS_REV not defined in device header file; using default!&quot;</span></div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;</div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;<span class="preprocessor">  #ifndef __MPU_PRESENT</span></div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;<span class="preprocessor">    #define __MPU_PRESENT             0U</span></div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;<span class="preprocessor">    #warning &quot;__MPU_PRESENT not defined in device header file; using default!&quot;</span></div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;</div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;<span class="preprocessor">  #ifndef __VTOR_PRESENT</span></div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;<span class="preprocessor">    #define __VTOR_PRESENT            0U</span></div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;<span class="preprocessor">    #warning &quot;__VTOR_PRESENT not defined in device header file; using default!&quot;</span></div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00149"></a><span class="lineno">  149</span>&#160;</div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;<span class="preprocessor">  #ifndef __NVIC_PRIO_BITS</span></div><div class="line"><a name="l00151"></a><span class="lineno">  151</span>&#160;<span class="preprocessor">    #define __NVIC_PRIO_BITS          2U</span></div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;<span class="preprocessor">    #warning &quot;__NVIC_PRIO_BITS not defined in device header file; using default!&quot;</span></div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;</div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;<span class="preprocessor">  #ifndef __Vendor_SysTickConfig</span></div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;<span class="preprocessor">    #define __Vendor_SysTickConfig    0U</span></div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;<span class="preprocessor">    #warning &quot;__Vendor_SysTickConfig not defined in device header file; using default!&quot;</span></div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;</div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;<span class="comment">/* IO definitions (access restrictions to peripheral registers) */</span></div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;<span class="preprocessor">  #define   __I     volatile             </span></div><div class="line"><a name="l00171"></a><span class="lineno">  171</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#af63697ed9952cc71e1225efe205f6cd3">  172</a></span>&#160;<span class="preprocessor">  #define   __I     volatile const       </span></div><div class="line"><a name="l00173"></a><span class="lineno">  173</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#a7e25d9380f9ef903923964322e71f2f6">  174</a></span>&#160;<span class="preprocessor">#define     __O     volatile             </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="core__cm0plus_8h.html#aec43007d9998a0a0e01faede4133d6be">  175</a></span>&#160;<span class="preprocessor">#define     __IO    volatile             </span></div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;<span class="preprocessor"></span><span class="comment">/* following defines should be used for structure members */</span><span class="preprocessor"></span></div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;<span class="preprocessor">#define     __IM     volatile const      </span></div><div class="line"><a name="l00179"></a><span class="lineno">  179</span>&#160;<span class="preprocessor">#define     __OM     volatile            </span></div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;<span class="preprocessor">#define     __IOM    volatile            </span></div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;<span class="preprocessor"></span></div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;<span class="preprocessor"></span><span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;<span class="comment"> *                 Register Abstraction</span></div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;<span class="comment">  Core Register contain:</span></div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;<span class="comment">  - Core Register</span></div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;<span class="comment">  - Core NVIC Register</span></div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;<span class="comment">  - Core SCB Register</span></div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;<span class="comment">  - Core SysTick Register</span></div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;<span class="comment">  - Core MPU Register</span></div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;<span class="comment"> ******************************************************************************/</span><span class="preprocessor"></span></div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;</div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html">  210</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">union</span></div><div class="line"><a name="l00211"></a><span class="lineno">  211</span>&#160;{</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;  <span class="keyword">struct</span></div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;  {</div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">  214</a></span>&#160;    uint32_t <a class="code" href="union_a_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">_reserved0</a>:28;              </div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#acd4a2b64faee91e4a9eef300667fa222">  215</a></span>&#160;    uint32_t <a class="code" href="union_a_p_s_r___type.html#acd4a2b64faee91e4a9eef300667fa222">V</a>:1;                        </div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a7a1caf92f32fe9ebd8d1fe89b06c7776">  216</a></span>&#160;    uint32_t <a class="code" href="union_a_p_s_r___type.html#a7a1caf92f32fe9ebd8d1fe89b06c7776">C</a>:1;                        </div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#a5ae954cbd9986cd64625d7fa00943c8e">  217</a></span>&#160;    uint32_t <a class="code" href="union_a_p_s_r___type.html#a5ae954cbd9986cd64625d7fa00943c8e">Z</a>:1;                        </div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#abae0610bc2a97bbf7f689e953e0b451f">  218</a></span>&#160;    uint32_t <a class="code" href="union_a_p_s_r___type.html#abae0610bc2a97bbf7f689e953e0b451f">N</a>:1;                        </div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;  } b;                                   </div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="union_a_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">  220</a></span>&#160;  uint32_t <a class="code" href="union_a_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">w</a>;                            </div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;} <a class="code" href="union_a_p_s_r___type.html">APSR_Type</a>;</div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;</div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;<span class="comment">/* APSR Register Definitions */</span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gac469528d210043c7bd3f12f0e6824766">  224</a></span>&#160;<span class="preprocessor">#define APSR_N_Pos                         31U                                            </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gadbc2cf55a026f661b53fadfcf822cef1">  225</a></span>&#160;<span class="preprocessor">#define APSR_N_Msk                         (1UL &lt;&lt; APSR_N_Pos)                            </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga3661286d108b1aca308d7445685eae3a">  227</a></span>&#160;<span class="preprocessor">#define APSR_Z_Pos                         30U                                            </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga1deb4d1aa72bb83d1f79329406f15711">  228</a></span>&#160;<span class="preprocessor">#define APSR_Z_Msk                         (1UL &lt;&lt; APSR_Z_Pos)                            </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga6cf72aa6f09a168f9e5beda1a4a887b9">  230</a></span>&#160;<span class="preprocessor">#define APSR_C_Pos                         29U                                            </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga6d47803fbad455bc10bd1ce59f2f335d">  231</a></span>&#160;<span class="preprocessor">#define APSR_C_Msk                         (1UL &lt;&lt; APSR_C_Pos)                            </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gac62830f67679ccd11658c4172c3e6ea7">  233</a></span>&#160;<span class="preprocessor">#define APSR_V_Pos                         28U                                            </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga33305d6701356bff6890b315fe8b5489">  234</a></span>&#160;<span class="preprocessor">#define APSR_V_Msk                         (1UL &lt;&lt; APSR_V_Pos)                            </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html">  240</a></span>&#160;<span class="preprocessor">typedef union</span></div><div class="line"><a name="l00241"></a><span class="lineno">  241</span>&#160;{</div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;  <span class="keyword">struct</span></div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;  {</div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html#ad502ba7dbb2aab5f87c782b28f02622d">  244</a></span>&#160;    uint32_t <a class="code" href="union_i_p_s_r___type.html#ad502ba7dbb2aab5f87c782b28f02622d">ISR</a>:9;                      </div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">  245</a></span>&#160;    uint32_t <a class="code" href="union_i_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">_reserved0</a>:23;              </div><div class="line"><a name="l00246"></a><span class="lineno">  246</span>&#160;  } b;                                   </div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="union_i_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">  247</a></span>&#160;  uint32_t <a class="code" href="union_i_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">w</a>;                            </div><div class="line"><a name="l00248"></a><span class="lineno">  248</span>&#160;} <a class="code" href="union_i_p_s_r___type.html">IPSR_Type</a>;</div><div class="line"><a name="l00249"></a><span class="lineno">  249</span>&#160;</div><div class="line"><a name="l00250"></a><span class="lineno">  250</span>&#160;<span class="comment">/* IPSR Register Definitions */</span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga0e34027584d02c43811ae908a5ca9adf">  251</a></span>&#160;<span class="preprocessor">#define IPSR_ISR_Pos                        0U                                            </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gaf013a4579a64d1f21f56ea9f1b33ab56">  252</a></span>&#160;<span class="preprocessor">#define IPSR_ISR_Msk                       (0x1FFUL </span><span class="comment">/*&lt;&lt; IPSR_ISR_Pos*/</span><span class="preprocessor">)                  </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html">  258</a></span>&#160;<span class="preprocessor">typedef union</span></div><div class="line"><a name="l00259"></a><span class="lineno">  259</span>&#160;{</div><div class="line"><a name="l00260"></a><span class="lineno">  260</span>&#160;  <span class="keyword">struct</span></div><div class="line"><a name="l00261"></a><span class="lineno">  261</span>&#160;  {</div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#ad502ba7dbb2aab5f87c782b28f02622d">  262</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#ad502ba7dbb2aab5f87c782b28f02622d">ISR</a>:9;                      </div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">  263</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">_reserved0</a>:15;              </div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a6e1cf12e53a20224f6f62c001d9be972">  264</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#a6e1cf12e53a20224f6f62c001d9be972">T</a>:1;                        </div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a959a73d8faee56599b7e792a7c5a2d16">  265</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#a959a73d8faee56599b7e792a7c5a2d16">_reserved1</a>:3;               </div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#acd4a2b64faee91e4a9eef300667fa222">  266</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#acd4a2b64faee91e4a9eef300667fa222">V</a>:1;                        </div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a7a1caf92f32fe9ebd8d1fe89b06c7776">  267</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#a7a1caf92f32fe9ebd8d1fe89b06c7776">C</a>:1;                        </div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#a5ae954cbd9986cd64625d7fa00943c8e">  268</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#a5ae954cbd9986cd64625d7fa00943c8e">Z</a>:1;                        </div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#abae0610bc2a97bbf7f689e953e0b451f">  269</a></span>&#160;    uint32_t <a class="code" href="unionx_p_s_r___type.html#abae0610bc2a97bbf7f689e953e0b451f">N</a>:1;                        </div><div class="line"><a name="l00270"></a><span class="lineno">  270</span>&#160;  } b;                                   </div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="unionx_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">  271</a></span>&#160;  uint32_t <a class="code" href="unionx_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">w</a>;                            </div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;} <a class="code" href="unionx_p_s_r___type.html">xPSR_Type</a>;</div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;</div><div class="line"><a name="l00274"></a><span class="lineno">  274</span>&#160;<span class="comment">/* xPSR Register Definitions */</span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga031eb1b8ebcdb3d602d0b9f2ec82a7ae">  275</a></span>&#160;<span class="preprocessor">#define xPSR_N_Pos                         31U                                            </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gaf600f4ff41b62cf2f3b0a59b6d2e93d6">  276</a></span>&#160;<span class="preprocessor">#define xPSR_N_Msk                         (1UL &lt;&lt; xPSR_N_Pos)                            </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga5869dd608eea73c80f0567d781d2230b">  278</a></span>&#160;<span class="preprocessor">#define xPSR_Z_Pos                         30U                                            </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga907599209fba99f579778e662021c4f2">  279</a></span>&#160;<span class="preprocessor">#define xPSR_Z_Msk                         (1UL &lt;&lt; xPSR_Z_Pos)                            </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga14adb79b91f6634b351a1b57394e2db6">  281</a></span>&#160;<span class="preprocessor">#define xPSR_C_Pos                         29U                                            </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga21e2497255d380f956ca0f48d11d0775">  282</a></span>&#160;<span class="preprocessor">#define xPSR_C_Msk                         (1UL &lt;&lt; xPSR_C_Pos)                            </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gae0cfbb394490db402623d97e6a979e00">  284</a></span>&#160;<span class="preprocessor">#define xPSR_V_Pos                         28U                                            </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gab07f94ed3b6ee695f5af719dc27995c2">  285</a></span>&#160;<span class="preprocessor">#define xPSR_V_Msk                         (1UL &lt;&lt; xPSR_V_Pos)                            </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga98d801da9a49cda944f52aeae104dd38">  287</a></span>&#160;<span class="preprocessor">#define xPSR_T_Pos                         24U                                            </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga30ae2111816e82d47636a8d4577eb6ee">  288</a></span>&#160;<span class="preprocessor">#define xPSR_T_Msk                         (1UL &lt;&lt; xPSR_T_Pos)                            </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga21bff245fb1aef9683f693d9d7bb2233">  290</a></span>&#160;<span class="preprocessor">#define xPSR_ISR_Pos                        0U                                            </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gadf8eed87e0081dfe1ef1c78a0ea91afd">  291</a></span>&#160;<span class="preprocessor">#define xPSR_ISR_Msk                       (0x1FFUL </span><span class="comment">/*&lt;&lt; xPSR_ISR_Pos*/</span><span class="preprocessor">)                  </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html">  297</a></span>&#160;<span class="preprocessor">typedef union</span></div><div class="line"><a name="l00298"></a><span class="lineno">  298</span>&#160;{</div><div class="line"><a name="l00299"></a><span class="lineno">  299</span>&#160;  <span class="keyword">struct</span></div><div class="line"><a name="l00300"></a><span class="lineno">  300</span>&#160;  {</div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#a2a6e513e8a6bf4e58db169e312172332">  301</a></span>&#160;    uint32_t <a class="code" href="union_c_o_n_t_r_o_l___type.html#a2a6e513e8a6bf4e58db169e312172332">nPRIV</a>:1;                    </div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#ae185aac93686ffc78e998a9daf41415b">  302</a></span>&#160;    uint32_t <a class="code" href="union_c_o_n_t_r_o_l___type.html#ae185aac93686ffc78e998a9daf41415b">SPSEL</a>:1;                    </div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#a959a73d8faee56599b7e792a7c5a2d16">  303</a></span>&#160;    uint32_t <a class="code" href="union_c_o_n_t_r_o_l___type.html#a959a73d8faee56599b7e792a7c5a2d16">_reserved1</a>:30;              </div><div class="line"><a name="l00304"></a><span class="lineno">  304</span>&#160;  } b;                                   </div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="union_c_o_n_t_r_o_l___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">  305</a></span>&#160;  uint32_t <a class="code" href="union_c_o_n_t_r_o_l___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">w</a>;                            </div><div class="line"><a name="l00306"></a><span class="lineno">  306</span>&#160;} <a class="code" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a>;</div><div class="line"><a name="l00307"></a><span class="lineno">  307</span>&#160;</div><div class="line"><a name="l00308"></a><span class="lineno">  308</span>&#160;<span class="comment">/* CONTROL Register Definitions */</span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga07eafc53e609895342c6a530e9d01310">  309</a></span>&#160;<span class="preprocessor">#define CONTROL_SPSEL_Pos                   1U                                            </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga70b29840969b06909da21369b0b05b53">  310</a></span>&#160;<span class="preprocessor">#define CONTROL_SPSEL_Msk                  (1UL &lt;&lt; CONTROL_SPSEL_Pos)                     </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#ga51b95bc03ec0d815b459bde0b14a5908">  312</a></span>&#160;<span class="preprocessor">#define CONTROL_nPRIV_Pos                   0U                                            </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___c_o_r_e.html#gaef3b20d77acb213338f89ce5e7bc36b0">  313</a></span>&#160;<span class="preprocessor">#define CONTROL_nPRIV_Msk                  (1UL </span><span class="comment">/*&lt;&lt; CONTROL_nPRIV_Pos*/</span><span class="preprocessor">)                 </span></div><div class="line"><a name="l00315"></a><span class="lineno">  315</span>&#160;<span class="preprocessor"></span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html">  328</a></span>&#160;<span class="preprocessor">typedef struct</span></div><div class="line"><a name="l00329"></a><span class="lineno">  329</span>&#160;{</div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#ab608972d2d0184ba03dc9f4f3fff4f06">  330</a></span>&#160;  __IOM uint32_t ISER[1U];               </div><div class="line"><a name="l00331"></a><span class="lineno">  331</span>&#160;        uint32_t RESERVED0[31U];</div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a6322dd58262ec1a7ea15765d9a8b5e70">  332</a></span>&#160;  __IOM uint32_t ICER[1U];               </div><div class="line"><a name="l00333"></a><span class="lineno">  333</span>&#160;        uint32_t RSERVED1[31U];</div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a39391701e1ec375637074dd76a35276f">  334</a></span>&#160;  __IOM uint32_t ISPR[1U];               </div><div class="line"><a name="l00335"></a><span class="lineno">  335</span>&#160;        uint32_t RESERVED2[31U];</div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a53f4282d43d93f2ddb19764f336ad27d">  336</a></span>&#160;  __IOM uint32_t ICPR[1U];               </div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;        uint32_t RESERVED3[31U];</div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;        uint32_t RESERVED4[64U];</div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="struct_n_v_i_c___type.html#a54051f32091607a64e1e044413da3b8b">  339</a></span>&#160;  __IOM uint32_t IP[8U];                 </div><div class="line"><a name="l00340"></a><span class="lineno">  340</span>&#160;}  <a class="code" href="struct_n_v_i_c___type.html">NVIC_Type</a>;</div><div class="line"><a name="l00341"></a><span class="lineno">  341</span>&#160;</div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html">  355</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct</span></div><div class="line"><a name="l00356"></a><span class="lineno">  356</span>&#160;{</div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#adbf8292503748ba6421a523bdee6819d">  357</a></span>&#160;  __IM  uint32_t CPUID;                  </div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#aced895d6aba03d72b0d865fcc5ce44ee">  358</a></span>&#160;  __IOM uint32_t ICSR;                   </div><div class="line"><a name="l00359"></a><span class="lineno">  359</span>&#160;<span class="preprocessor">#if defined (__VTOR_PRESENT) &amp;&amp; (__VTOR_PRESENT == 1U)</span></div><div class="line"><a name="l00360"></a><span class="lineno">  360</span>&#160;  __IOM uint32_t VTOR;                   </div><div class="line"><a name="l00361"></a><span class="lineno">  361</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00362"></a><span class="lineno">  362</span>&#160;        uint32_t RESERVED0;</div><div class="line"><a name="l00363"></a><span class="lineno">  363</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a9b6ccd9c0c0865f8facad77ea37240b0">  364</a></span>&#160;  __IOM uint32_t AIRCR;                  </div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#acac65f229cb3fcb5369a0a9e0393b8c0">  365</a></span>&#160;  __IOM uint32_t SCR;                    </div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#ad68b5c1f2d9845ef4247cf2d9b041336">  366</a></span>&#160;  __IOM uint32_t CCR;                    </div><div class="line"><a name="l00367"></a><span class="lineno">  367</span>&#160;        uint32_t RESERVED1;</div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a9976ebb49caa4da93e1dad137071b9ee">  368</a></span>&#160;  __IOM uint32_t SHP[2U];                </div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="struct_s_c_b___type.html#a44ad5c292dbd77e72f310902375a8a06">  369</a></span>&#160;  __IOM uint32_t SHCSR;                  </div><div class="line"><a name="l00370"></a><span class="lineno">  370</span>&#160;} <a class="code" href="struct_s_c_b___type.html">SCB_Type</a>;</div><div class="line"><a name="l00371"></a><span class="lineno">  371</span>&#160;</div><div class="line"><a name="l00372"></a><span class="lineno">  372</span>&#160;<span class="comment">/* SCB CPUID Register Definitions */</span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga58686b88f94f789d4e6f429fe1ff58cf">  373</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga0932b31faafd47656a03ced75a31d99b">  374</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL &lt;&lt; SCB_CPUID_IMPLEMENTER_Pos)          </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga104462bd0815391b4044a70bd15d3a71">  376</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_VARIANT_Pos              20U                                            </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gad358dfbd04300afc1824329d128b99e8">  377</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_VARIANT_Msk              (0xFUL &lt;&lt; SCB_CPUID_VARIANT_Pos)               </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaf8b3236b08fb8e840efb682645fb0e98">  379</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gafae4a1f27a927338ae9dc51a0e146213">  380</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL &lt;&lt; SCB_CPUID_ARCHITECTURE_Pos)          </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga705f68eaa9afb042ca2407dc4e4629ac">  382</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_PARTNO_Pos                4U                                            </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga98e581423ca016680c238c469aba546d">  383</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_PARTNO_Msk               (0xFFFUL &lt;&lt; SCB_CPUID_PARTNO_Pos)              </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3c3d9071e574de11fb27ba57034838b1">  385</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_REVISION_Pos              0U                                            </span></div><div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga2ec0448b6483f77e7f5d08b4b81d85df">  386</a></span>&#160;<span class="preprocessor">#define SCB_CPUID_REVISION_Msk             (0xFUL </span><span class="comment">/*&lt;&lt; SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">)          </span></div><div class="line"><a name="l00388"></a><span class="lineno">  388</span>&#160;<span class="preprocessor"></span><span class="comment">/* SCB Interrupt Control State Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga750d4b52624a46d71356db4ea769573b">  389</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Pos            31U                                            </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga340e3f79e9c3607dee9f2c048b6b22e8">  390</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_NMIPENDSET_Msk            (1UL &lt;&lt; SCB_ICSR_NMIPENDSET_Pos)               </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab5ded23d2ab1d5ff7cc7ce746205e9fe">  392</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSVSET_Pos             28U                                            </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga1e40d93efb402763c8c00ddcc56724ff">  393</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSVSET_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSVSET_Pos)                </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae218d9022288f89faf57187c4d542ecd">  395</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Pos             27U                                            </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga4a901ace381d3c1c74ac82b22fae2e1e">  396</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSVCLR_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSVCLR_Pos)                </span></div><div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga9dbb3358c6167c9c3f85661b90fb2794">  398</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSTSET_Pos             26U                                            </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga7325b61ea0ec323ef2d5c893b112e546">  399</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSTSET_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSTSET_Pos)                </span></div><div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gadbe25e4b333ece1341beb1a740168fdc">  401</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Pos             25U                                            </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab241827d2a793269d8cd99b9b28c2157">  402</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_PENDSTCLR_Msk             (1UL &lt;&lt; SCB_ICSR_PENDSTCLR_Pos)                </span></div><div class="line"><a name="l00404"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga11cb5b1f9ce167b81f31787a77e575df">  404</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            </span></div><div class="line"><a name="l00405"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaa966600396290808d596fe96e92ca2b5">  405</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_ISRPREEMPT_Msk            (1UL &lt;&lt; SCB_ICSR_ISRPREEMPT_Pos)               </span></div><div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga10749d92b9b744094b845c2eb46d4319">  407</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_ISRPENDING_Pos            22U                                            </span></div><div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga056d74fd538e5d36d3be1f28d399c877">  408</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_ISRPENDING_Msk            (1UL &lt;&lt; SCB_ICSR_ISRPENDING_Pos)               </span></div><div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gada60c92bf88d6fd21a8f49efa4a127b8">  410</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_VECTPENDING_Pos           12U                                            </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gacb6992e7c7ddc27a370f62878a21ef72">  411</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL &lt;&lt; SCB_ICSR_VECTPENDING_Pos)          </span></div><div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gae4f602c7c5c895d5fb687b71b0979fc3">  413</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Pos             0U                                            </span></div><div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga5533791a4ecf1b9301c883047b3e8396">  414</a></span>&#160;<span class="preprocessor">#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL </span><span class="comment">/*&lt;&lt; SCB_ICSR_VECTACTIVE_Pos*/</span><span class="preprocessor">)       </span></div><div class="line"><a name="l00416"></a><span class="lineno">  416</span>&#160;<span class="preprocessor">#if defined (__VTOR_PRESENT) &amp;&amp; (__VTOR_PRESENT == 1U)</span></div><div class="line"><a name="l00417"></a><span class="lineno">  417</span>&#160;<span class="comment">/* SCB Interrupt Control State Register Definitions */</span></div><div class="line"><a name="l00418"></a><span class="lineno">  418</span>&#160;<span class="preprocessor">#define SCB_VTOR_TBLOFF_Pos                 8U                                            </span></div><div class="line"><a name="l00419"></a><span class="lineno">  419</span>&#160;<span class="preprocessor">#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL &lt;&lt; SCB_VTOR_TBLOFF_Pos)            </span></div><div class="line"><a name="l00420"></a><span class="lineno">  420</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00421"></a><span class="lineno">  421</span>&#160;</div><div class="line"><a name="l00422"></a><span class="lineno">  422</span>&#160;<span class="comment">/* SCB Application Interrupt and Reset Control Register Definitions */</span></div><div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">  423</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_VECTKEY_Pos              16U                                            </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga90c7cf0c490e7ae55f9503a7fda1dd22">  424</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL &lt;&lt; SCB_AIRCR_VECTKEY_Pos)            </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaec404750ff5ca07f499a3c06b62051ef">  426</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            </span></div><div class="line"><a name="l00427"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gabacedaefeefc73d666bbe59ece904493">  427</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL &lt;&lt; SCB_AIRCR_VECTKEYSTAT_Pos)        </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gad31dec98fbc0d33ace63cb1f1a927923">  429</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Pos            15U                                            </span></div><div class="line"><a name="l00430"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga2f571f93d3d4a6eac9a3040756d3d951">  430</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_ENDIANESS_Msk            (1UL &lt;&lt; SCB_AIRCR_ENDIANESS_Pos)               </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaffb2737eca1eac0fc1c282a76a40953c">  432</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            </span></div><div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">  433</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL &lt;&lt; SCB_AIRCR_SYSRESETREQ_Pos)             </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gaa30a12e892bb696e61626d71359a9029">  435</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            </span></div><div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga212c5ab1c1c82c807d30d2307aa8d218">  436</a></span>&#160;<span class="preprocessor">#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL &lt;&lt; SCB_AIRCR_VECTCLRACTIVE_Pos)           </span></div><div class="line"><a name="l00438"></a><span class="lineno">  438</span>&#160;<span class="preprocessor"></span><span class="comment">/* SCB System Control Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3bddcec40aeaf3d3a998446100fa0e44">  439</a></span>&#160;<span class="preprocessor">#define SCB_SCR_SEVONPEND_Pos               4U                                            </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gafb98656644a14342e467505f69a997c9">  440</a></span>&#160;<span class="preprocessor">#define SCB_SCR_SEVONPEND_Msk              (1UL &lt;&lt; SCB_SCR_SEVONPEND_Pos)                 </span></div><div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gab304f6258ec03bd9a6e7a360515c3cfe">  442</a></span>&#160;<span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Pos               2U                                            </span></div><div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga77c06a69c63f4b3f6ec1032e911e18e7">  443</a></span>&#160;<span class="preprocessor">#define SCB_SCR_SLEEPDEEP_Msk              (1UL &lt;&lt; SCB_SCR_SLEEPDEEP_Pos)                 </span></div><div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga3680a15114d7fdc1e25043b881308fe9">  445</a></span>&#160;<span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            </span></div><div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga50a243e317b9a70781b02758d45b05ee">  446</a></span>&#160;<span class="preprocessor">#define SCB_SCR_SLEEPONEXIT_Msk            (1UL &lt;&lt; SCB_SCR_SLEEPONEXIT_Pos)               </span></div><div class="line"><a name="l00448"></a><span class="lineno">  448</span>&#160;<span class="preprocessor"></span><span class="comment">/* SCB Configuration Control Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac2d20a250960a432cc74da59d20e2f86">  449</a></span>&#160;<span class="preprocessor">#define SCB_CCR_STKALIGN_Pos                9U                                            </span></div><div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga33cf22d3d46af158a03aad25ddea1bcb">  450</a></span>&#160;<span class="preprocessor">#define SCB_CCR_STKALIGN_Msk               (1UL &lt;&lt; SCB_CCR_STKALIGN_Pos)                  </span></div><div class="line"><a name="l00452"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#gac4e4928b864ea10fc24dbbc57d976229">  452</a></span>&#160;<span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            </span></div><div class="line"><a name="l00453"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga68c96ad594af70c007923979085c99e0">  453</a></span>&#160;<span class="preprocessor">#define SCB_CCR_UNALIGN_TRP_Msk            (1UL &lt;&lt; SCB_CCR_UNALIGN_TRP_Pos)               </span></div><div class="line"><a name="l00455"></a><span class="lineno">  455</span>&#160;<span class="preprocessor"></span><span class="comment">/* SCB System Handler Control and State Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga2f93ec9b243f94cdd3e94b8f0bf43641">  456</a></span>&#160;<span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            </span></div><div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___s_c_b.html#ga6095a7acfbad66f52822b1392be88652">  457</a></span>&#160;<span class="preprocessor">#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL &lt;&lt; SCB_SHCSR_SVCALLPENDED_Pos)            </span></div><div class="line"><a name="l00459"></a><span class="lineno">  459</span>&#160;<span class="preprocessor"></span></div><div class="line"><a name="l00472"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html">  472</a></span>&#160;<span class="preprocessor">typedef struct</span></div><div class="line"><a name="l00473"></a><span class="lineno">  473</span>&#160;{</div><div class="line"><a name="l00474"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#ac81efc171e9852a36caeb47122bfec5b">  474</a></span>&#160;  __IOM uint32_t CTRL;                   </div><div class="line"><a name="l00475"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#a0c1333686137b7e25a46bd548a5b5bc3">  475</a></span>&#160;  __IOM uint32_t LOAD;                   </div><div class="line"><a name="l00476"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#ae7a655a853654127f3dfb7fa32c3f457">  476</a></span>&#160;  __IOM uint32_t VAL;                    </div><div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="struct_sys_tick___type.html#aedf0dff29a9cacdaa2fb7eec6b116a13">  477</a></span>&#160;  __IM  uint32_t CALIB;                  </div><div class="line"><a name="l00478"></a><span class="lineno">  478</span>&#160;} <a class="code" href="struct_sys_tick___type.html">SysTick_Type</a>;</div><div class="line"><a name="l00479"></a><span class="lineno">  479</span>&#160;</div><div class="line"><a name="l00480"></a><span class="lineno">  480</span>&#160;<span class="comment">/* SysTick Control / Status Register Definitions */</span></div><div class="line"><a name="l00481"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gadbb65d4a815759649db41df216ed4d60">  481</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            </span></div><div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga1bf3033ecccf200f59baefe15dbb367c">  482</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_COUNTFLAG_Msk         (1UL &lt;&lt; SysTick_CTRL_COUNTFLAG_Pos)            </span></div><div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga24fbc69a5f0b78d67fda2300257baff1">  484</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373">  485</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_CLKSOURCE_Msk         (1UL &lt;&lt; SysTick_CTRL_CLKSOURCE_Pos)            </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga88f45bbb89ce8df3cd2b2613c7b48214">  487</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_TICKINT_Pos            1U                                            </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027">  488</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_TICKINT_Msk           (1UL &lt;&lt; SysTick_CTRL_TICKINT_Pos)              </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga0b48cc1e36d92a92e4bf632890314810">  490</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_ENABLE_Pos             0U                                            </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">  491</a></span>&#160;<span class="preprocessor">#define SysTick_CTRL_ENABLE_Msk            (1UL </span><span class="comment">/*&lt;&lt; SysTick_CTRL_ENABLE_Pos*/</span><span class="preprocessor">)           </span></div><div class="line"><a name="l00493"></a><span class="lineno">  493</span>&#160;<span class="preprocessor"></span><span class="comment">/* SysTick Reload Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gaf44d10df359dc5bf5752b0894ae3bad2">  494</a></span>&#160;<span class="preprocessor">#define SysTick_LOAD_RELOAD_Pos             0U                                            </span></div><div class="line"><a name="l00495"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">  495</a></span>&#160;<span class="preprocessor">#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL </span><span class="comment">/*&lt;&lt; SysTick_LOAD_RELOAD_Pos*/</span><span class="preprocessor">)    </span></div><div class="line"><a name="l00497"></a><span class="lineno">  497</span>&#160;<span class="preprocessor"></span><span class="comment">/* SysTick Current Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga3208104c3b019b5de35ae8c21d5c34dd">  498</a></span>&#160;<span class="preprocessor">#define SysTick_VAL_CURRENT_Pos             0U                                            </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gafc77b56d568930b49a2474debc75ab45">  499</a></span>&#160;<span class="preprocessor">#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL </span><span class="comment">/*&lt;&lt; SysTick_VAL_CURRENT_Pos*/</span><span class="preprocessor">)    </span></div><div class="line"><a name="l00501"></a><span class="lineno">  501</span>&#160;<span class="preprocessor"></span><span class="comment">/* SysTick Calibration Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga534dbe414e7a46a6ce4c1eca1fbff409">  502</a></span>&#160;<span class="preprocessor">#define SysTick_CALIB_NOREF_Pos            31U                                            </span></div><div class="line"><a name="l00503"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga3af0d891fdd99bcc8d8912d37830edb6">  503</a></span>&#160;<span class="preprocessor">#define SysTick_CALIB_NOREF_Msk            (1UL &lt;&lt; SysTick_CALIB_NOREF_Pos)               </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gadd0c9cd6641b9f6a0c618e7982954860">  505</a></span>&#160;<span class="preprocessor">#define SysTick_CALIB_SKEW_Pos             30U                                            </span></div><div class="line"><a name="l00506"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#ga8a6a85a87334776f33d77fd147587431">  506</a></span>&#160;<span class="preprocessor">#define SysTick_CALIB_SKEW_Msk             (1UL &lt;&lt; SysTick_CALIB_SKEW_Pos)                </span></div><div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gacae558f6e75a0bed5d826f606d8e695e">  508</a></span>&#160;<span class="preprocessor">#define SysTick_CALIB_TENMS_Pos             0U                                            </span></div><div class="line"><a name="l00509"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___sys_tick.html#gaf1e68865c5aece2ad58971225bd3e95e">  509</a></span>&#160;<span class="preprocessor">#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL </span><span class="comment">/*&lt;&lt; SysTick_CALIB_TENMS_Pos*/</span><span class="preprocessor">)    </span></div><div class="line"><a name="l00511"></a><span class="lineno">  511</span>&#160;<span class="preprocessor"></span></div><div class="line"><a name="l00513"></a><span class="lineno">  513</span>&#160;<span class="preprocessor">#if defined (__MPU_PRESENT) &amp;&amp; (__MPU_PRESENT == 1U)</span></div><div class="line"><a name="l00514"></a><span class="lineno">  514</span>&#160;</div><div class="line"><a name="l00524"></a><span class="lineno">  524</span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct</span></div><div class="line"><a name="l00525"></a><span class="lineno">  525</span>&#160;{</div><div class="line"><a name="l00526"></a><span class="lineno">  526</span>&#160;  __IM  uint32_t TYPE;                   </div><div class="line"><a name="l00527"></a><span class="lineno">  527</span>&#160;  __IOM uint32_t CTRL;                   </div><div class="line"><a name="l00528"></a><span class="lineno">  528</span>&#160;  __IOM uint32_t RNR;                    </div><div class="line"><a name="l00529"></a><span class="lineno">  529</span>&#160;  __IOM uint32_t RBAR;                   </div><div class="line"><a name="l00530"></a><span class="lineno">  530</span>&#160;  __IOM uint32_t RASR;                   </div><div class="line"><a name="l00531"></a><span class="lineno">  531</span>&#160;} MPU_Type;</div><div class="line"><a name="l00532"></a><span class="lineno">  532</span>&#160;</div><div class="line"><a name="l00533"></a><span class="lineno">  533</span>&#160;<span class="preprocessor">#define MPU_TYPE_RALIASES                  1U</span></div><div class="line"><a name="l00534"></a><span class="lineno">  534</span>&#160;</div><div class="line"><a name="l00535"></a><span class="lineno">  535</span>&#160;<span class="comment">/* MPU Type Register Definitions */</span></div><div class="line"><a name="l00536"></a><span class="lineno">  536</span>&#160;<span class="preprocessor">#define MPU_TYPE_IREGION_Pos               16U                                            </span></div><div class="line"><a name="l00537"></a><span class="lineno">  537</span>&#160;<span class="preprocessor">#define MPU_TYPE_IREGION_Msk               (0xFFUL &lt;&lt; MPU_TYPE_IREGION_Pos)               </span></div><div class="line"><a name="l00539"></a><span class="lineno">  539</span>&#160;<span class="preprocessor">#define MPU_TYPE_DREGION_Pos                8U                                            </span></div><div class="line"><a name="l00540"></a><span class="lineno">  540</span>&#160;<span class="preprocessor">#define MPU_TYPE_DREGION_Msk               (0xFFUL &lt;&lt; MPU_TYPE_DREGION_Pos)               </span></div><div class="line"><a name="l00542"></a><span class="lineno">  542</span>&#160;<span class="preprocessor">#define MPU_TYPE_SEPARATE_Pos               0U                                            </span></div><div class="line"><a name="l00543"></a><span class="lineno">  543</span>&#160;<span class="preprocessor">#define MPU_TYPE_SEPARATE_Msk              (1UL </span><span class="comment">/*&lt;&lt; MPU_TYPE_SEPARATE_Pos*/</span><span class="preprocessor">)             </span></div><div class="line"><a name="l00545"></a><span class="lineno">  545</span>&#160;<span class="preprocessor"></span><span class="comment">/* MPU Control Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00546"></a><span class="lineno">  546</span>&#160;<span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            </span></div><div class="line"><a name="l00547"></a><span class="lineno">  547</span>&#160;<span class="preprocessor">#define MPU_CTRL_PRIVDEFENA_Msk            (1UL &lt;&lt; MPU_CTRL_PRIVDEFENA_Pos)               </span></div><div class="line"><a name="l00549"></a><span class="lineno">  549</span>&#160;<span class="preprocessor">#define MPU_CTRL_HFNMIENA_Pos               1U                                            </span></div><div class="line"><a name="l00550"></a><span class="lineno">  550</span>&#160;<span class="preprocessor">#define MPU_CTRL_HFNMIENA_Msk              (1UL &lt;&lt; MPU_CTRL_HFNMIENA_Pos)                 </span></div><div class="line"><a name="l00552"></a><span class="lineno">  552</span>&#160;<span class="preprocessor">#define MPU_CTRL_ENABLE_Pos                 0U                                            </span></div><div class="line"><a name="l00553"></a><span class="lineno">  553</span>&#160;<span class="preprocessor">#define MPU_CTRL_ENABLE_Msk                (1UL </span><span class="comment">/*&lt;&lt; MPU_CTRL_ENABLE_Pos*/</span><span class="preprocessor">)               </span></div><div class="line"><a name="l00555"></a><span class="lineno">  555</span>&#160;<span class="preprocessor"></span><span class="comment">/* MPU Region Number Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00556"></a><span class="lineno">  556</span>&#160;<span class="preprocessor">#define MPU_RNR_REGION_Pos                  0U                                            </span></div><div class="line"><a name="l00557"></a><span class="lineno">  557</span>&#160;<span class="preprocessor">#define MPU_RNR_REGION_Msk                 (0xFFUL </span><span class="comment">/*&lt;&lt; MPU_RNR_REGION_Pos*/</span><span class="preprocessor">)             </span></div><div class="line"><a name="l00559"></a><span class="lineno">  559</span>&#160;<span class="preprocessor"></span><span class="comment">/* MPU Region Base Address Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00560"></a><span class="lineno">  560</span>&#160;<span class="preprocessor">#define MPU_RBAR_ADDR_Pos                   8U                                            </span></div><div class="line"><a name="l00561"></a><span class="lineno">  561</span>&#160;<span class="preprocessor">#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL &lt;&lt; MPU_RBAR_ADDR_Pos)              </span></div><div class="line"><a name="l00563"></a><span class="lineno">  563</span>&#160;<span class="preprocessor">#define MPU_RBAR_VALID_Pos                  4U                                            </span></div><div class="line"><a name="l00564"></a><span class="lineno">  564</span>&#160;<span class="preprocessor">#define MPU_RBAR_VALID_Msk                 (1UL &lt;&lt; MPU_RBAR_VALID_Pos)                    </span></div><div class="line"><a name="l00566"></a><span class="lineno">  566</span>&#160;<span class="preprocessor">#define MPU_RBAR_REGION_Pos                 0U                                            </span></div><div class="line"><a name="l00567"></a><span class="lineno">  567</span>&#160;<span class="preprocessor">#define MPU_RBAR_REGION_Msk                (0xFUL </span><span class="comment">/*&lt;&lt; MPU_RBAR_REGION_Pos*/</span><span class="preprocessor">)             </span></div><div class="line"><a name="l00569"></a><span class="lineno">  569</span>&#160;<span class="preprocessor"></span><span class="comment">/* MPU Region Attribute and Size Register Definitions */</span><span class="preprocessor"></span></div><div class="line"><a name="l00570"></a><span class="lineno">  570</span>&#160;<span class="preprocessor">#define MPU_RASR_ATTRS_Pos                 16U                                            </span></div><div class="line"><a name="l00571"></a><span class="lineno">  571</span>&#160;<span class="preprocessor">#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL &lt;&lt; MPU_RASR_ATTRS_Pos)               </span></div><div class="line"><a name="l00573"></a><span class="lineno">  573</span>&#160;<span class="preprocessor">#define MPU_RASR_XN_Pos                    28U                                            </span></div><div class="line"><a name="l00574"></a><span class="lineno">  574</span>&#160;<span class="preprocessor">#define MPU_RASR_XN_Msk                    (1UL &lt;&lt; MPU_RASR_XN_Pos)                       </span></div><div class="line"><a name="l00576"></a><span class="lineno">  576</span>&#160;<span class="preprocessor">#define MPU_RASR_AP_Pos                    24U                                            </span></div><div class="line"><a name="l00577"></a><span class="lineno">  577</span>&#160;<span class="preprocessor">#define MPU_RASR_AP_Msk                    (0x7UL &lt;&lt; MPU_RASR_AP_Pos)                     </span></div><div class="line"><a name="l00579"></a><span class="lineno">  579</span>&#160;<span class="preprocessor">#define MPU_RASR_TEX_Pos                   19U                                            </span></div><div class="line"><a name="l00580"></a><span class="lineno">  580</span>&#160;<span class="preprocessor">#define MPU_RASR_TEX_Msk                   (0x7UL &lt;&lt; MPU_RASR_TEX_Pos)                    </span></div><div class="line"><a name="l00582"></a><span class="lineno">  582</span>&#160;<span class="preprocessor">#define MPU_RASR_S_Pos                     18U                                            </span></div><div class="line"><a name="l00583"></a><span class="lineno">  583</span>&#160;<span class="preprocessor">#define MPU_RASR_S_Msk                     (1UL &lt;&lt; MPU_RASR_S_Pos)                        </span></div><div class="line"><a name="l00585"></a><span class="lineno">  585</span>&#160;<span class="preprocessor">#define MPU_RASR_C_Pos                     17U                                            </span></div><div class="line"><a name="l00586"></a><span class="lineno">  586</span>&#160;<span class="preprocessor">#define MPU_RASR_C_Msk                     (1UL &lt;&lt; MPU_RASR_C_Pos)                        </span></div><div class="line"><a name="l00588"></a><span class="lineno">  588</span>&#160;<span class="preprocessor">#define MPU_RASR_B_Pos                     16U                                            </span></div><div class="line"><a name="l00589"></a><span class="lineno">  589</span>&#160;<span class="preprocessor">#define MPU_RASR_B_Msk                     (1UL &lt;&lt; MPU_RASR_B_Pos)                        </span></div><div class="line"><a name="l00591"></a><span class="lineno">  591</span>&#160;<span class="preprocessor">#define MPU_RASR_SRD_Pos                    8U                                            </span></div><div class="line"><a name="l00592"></a><span class="lineno">  592</span>&#160;<span class="preprocessor">#define MPU_RASR_SRD_Msk                   (0xFFUL &lt;&lt; MPU_RASR_SRD_Pos)                   </span></div><div class="line"><a name="l00594"></a><span class="lineno">  594</span>&#160;<span class="preprocessor">#define MPU_RASR_SIZE_Pos                   1U                                            </span></div><div class="line"><a name="l00595"></a><span class="lineno">  595</span>&#160;<span class="preprocessor">#define MPU_RASR_SIZE_Msk                  (0x1FUL &lt;&lt; MPU_RASR_SIZE_Pos)                  </span></div><div class="line"><a name="l00597"></a><span class="lineno">  597</span>&#160;<span class="preprocessor">#define MPU_RASR_ENABLE_Pos                 0U                                            </span></div><div class="line"><a name="l00598"></a><span class="lineno">  598</span>&#160;<span class="preprocessor">#define MPU_RASR_ENABLE_Msk                (1UL </span><span class="comment">/*&lt;&lt; MPU_RASR_ENABLE_Pos*/</span><span class="preprocessor">)               </span></div><div class="line"><a name="l00600"></a><span class="lineno">  600</span>&#160;<span class="preprocessor"></span></div><div class="line"><a name="l00601"></a><span class="lineno">  601</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00602"></a><span class="lineno">  602</span>&#160;</div><div class="line"><a name="l00603"></a><span class="lineno">  603</span>&#160;</div><div class="line"><a name="l00611"></a><span class="lineno">  611</span>&#160;</div><div class="line"><a name="l00627"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__bitfield.html#ga286e3b913dbd236c7f48ea70c8821f4e">  627</a></span>&#160;<span class="preprocessor">#define _VAL2FLD(field, value)    (((uint32_t)(value) &lt;&lt; field ## _Pos) &amp; field ## _Msk)</span></div><div class="line"><a name="l00628"></a><span class="lineno">  628</span>&#160;</div><div class="line"><a name="l00635"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__bitfield.html#ga139b6e261c981f014f386927ca4a8444">  635</a></span>&#160;<span class="preprocessor">#define _FLD2VAL(field, value)    (((uint32_t)(value) &amp; field ## _Msk) &gt;&gt; field ## _Pos)</span></div><div class="line"><a name="l00636"></a><span class="lineno">  636</span>&#160;</div><div class="line"><a name="l00647"></a><span class="lineno">  647</span>&#160;<span class="comment">/* Memory mapping of Core Hardware */</span></div><div class="line"><a name="l00648"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga3c14ed93192c8d9143322bbf77ebf770">  648</a></span>&#160;<span class="preprocessor">#define SCS_BASE            (0xE000E000UL)                            </span></div><div class="line"><a name="l00649"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#ga58effaac0b93006b756d33209e814646">  649</a></span>&#160;<span class="preprocessor">#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    </span></div><div class="line"><a name="l00650"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gaa0288691785a5f868238e0468b39523d">  650</a></span>&#160;<span class="preprocessor">#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    </span></div><div class="line"><a name="l00651"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gad55a7ddb8d4b2398b0c1cfec76c0d9fd">  651</a></span>&#160;<span class="preprocessor">#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    </span></div><div class="line"><a name="l00653"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">  653</a></span>&#160;<span class="preprocessor">#define SCB                 ((SCB_Type       *)     SCB_BASE      )   </span></div><div class="line"><a name="l00654"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">  654</a></span>&#160;<span class="preprocessor">#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   </span></div><div class="line"><a name="l00655"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">  655</a></span>&#160;<span class="preprocessor">#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   </span></div><div class="line"><a name="l00657"></a><span class="lineno">  657</span>&#160;<span class="preprocessor">#if defined (__MPU_PRESENT) &amp;&amp; (__MPU_PRESENT == 1U)</span></div><div class="line"><a name="l00658"></a><span class="lineno">  658</span>&#160;<span class="preprocessor">  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    </span></div><div class="line"><a name="l00659"></a><span class="lineno">  659</span>&#160;<span class="preprocessor">  #define MPU               ((MPU_Type       *)     MPU_BASE      )   </span></div><div class="line"><a name="l00660"></a><span class="lineno">  660</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00661"></a><span class="lineno">  661</span>&#160;</div><div class="line"><a name="l00666"></a><span class="lineno">  666</span>&#160;<span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00667"></a><span class="lineno">  667</span>&#160;<span class="comment"> *                Hardware Abstraction Layer</span></div><div class="line"><a name="l00668"></a><span class="lineno">  668</span>&#160;<span class="comment">  Core Function Interface contains:</span></div><div class="line"><a name="l00669"></a><span class="lineno">  669</span>&#160;<span class="comment">  - Core NVIC Functions</span></div><div class="line"><a name="l00670"></a><span class="lineno">  670</span>&#160;<span class="comment">  - Core SysTick Functions</span></div><div class="line"><a name="l00671"></a><span class="lineno">  671</span>&#160;<span class="comment">  - Core Register Access Functions</span></div><div class="line"><a name="l00672"></a><span class="lineno">  672</span>&#160;<span class="comment"> ******************************************************************************/</span></div><div class="line"><a name="l00679"></a><span class="lineno">  679</span>&#160;<span class="comment">/* ##########################   NVIC functions  #################################### */</span></div><div class="line"><a name="l00687"></a><span class="lineno">  687</span>&#160;<span class="preprocessor">#ifdef CMSIS_NVIC_VIRTUAL</span></div><div class="line"><a name="l00688"></a><span class="lineno">  688</span>&#160;<span class="preprocessor">  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE</span></div><div class="line"><a name="l00689"></a><span class="lineno">  689</span>&#160;<span class="preprocessor">    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE &quot;cmsis_nvic_virtual.h&quot;</span></div><div class="line"><a name="l00690"></a><span class="lineno">  690</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00691"></a><span class="lineno">  691</span>&#160;<span class="preprocessor">  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE</span></div><div class="line"><a name="l00692"></a><span class="lineno">  692</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00693"></a><span class="lineno">  693</span>&#160;<span class="preprocessor">  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping</span></div><div class="line"><a name="l00694"></a><span class="lineno">  694</span>&#160;<span class="preprocessor">  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping</span></div><div class="line"><a name="l00695"></a><span class="lineno">  695</span>&#160;<span class="preprocessor">  #define NVIC_EnableIRQ              __NVIC_EnableIRQ</span></div><div class="line"><a name="l00696"></a><span class="lineno">  696</span>&#160;<span class="preprocessor">  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ</span></div><div class="line"><a name="l00697"></a><span class="lineno">  697</span>&#160;<span class="preprocessor">  #define NVIC_DisableIRQ             __NVIC_DisableIRQ</span></div><div class="line"><a name="l00698"></a><span class="lineno">  698</span>&#160;<span class="preprocessor">  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ</span></div><div class="line"><a name="l00699"></a><span class="lineno">  699</span>&#160;<span class="preprocessor">  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ</span></div><div class="line"><a name="l00700"></a><span class="lineno">  700</span>&#160;<span class="preprocessor">  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ</span></div><div class="line"><a name="l00701"></a><span class="lineno">  701</span>&#160;<span class="comment">/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */</span></div><div class="line"><a name="l00702"></a><span class="lineno">  702</span>&#160;<span class="preprocessor">  #define NVIC_SetPriority            __NVIC_SetPriority</span></div><div class="line"><a name="l00703"></a><span class="lineno">  703</span>&#160;<span class="preprocessor">  #define NVIC_GetPriority            __NVIC_GetPriority</span></div><div class="line"><a name="l00704"></a><span class="lineno">  704</span>&#160;<span class="preprocessor">  #define NVIC_SystemReset            __NVIC_SystemReset</span></div><div class="line"><a name="l00705"></a><span class="lineno">  705</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* CMSIS_NVIC_VIRTUAL */</span><span class="preprocessor"></span></div><div class="line"><a name="l00706"></a><span class="lineno">  706</span>&#160;</div><div class="line"><a name="l00707"></a><span class="lineno">  707</span>&#160;<span class="preprocessor">#ifdef CMSIS_VECTAB_VIRTUAL</span></div><div class="line"><a name="l00708"></a><span class="lineno">  708</span>&#160;<span class="preprocessor">  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE</span></div><div class="line"><a name="l00709"></a><span class="lineno">  709</span>&#160;<span class="preprocessor">    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE &quot;cmsis_vectab_virtual.h&quot;</span></div><div class="line"><a name="l00710"></a><span class="lineno">  710</span>&#160;<span class="preprocessor">  #endif</span></div><div class="line"><a name="l00711"></a><span class="lineno">  711</span>&#160;<span class="preprocessor">  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE</span></div><div class="line"><a name="l00712"></a><span class="lineno">  712</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00713"></a><span class="lineno">  713</span>&#160;<span class="preprocessor">  #define NVIC_SetVector              __NVIC_SetVector</span></div><div class="line"><a name="l00714"></a><span class="lineno">  714</span>&#160;<span class="preprocessor">  #define NVIC_GetVector              __NVIC_GetVector</span></div><div class="line"><a name="l00715"></a><span class="lineno">  715</span>&#160;<span class="preprocessor">#endif  </span><span class="comment">/* (CMSIS_VECTAB_VIRTUAL) */</span><span class="preprocessor"></span></div><div class="line"><a name="l00716"></a><span class="lineno">  716</span>&#160;</div><div class="line"><a name="l00717"></a><span class="lineno">  717</span>&#160;<span class="preprocessor">#define NVIC_USER_IRQ_OFFSET          16</span></div><div class="line"><a name="l00718"></a><span class="lineno">  718</span>&#160;</div><div class="line"><a name="l00719"></a><span class="lineno">  719</span>&#160;</div><div class="line"><a name="l00720"></a><span class="lineno">  720</span>&#160;<span class="comment">/* The following EXC_RETURN values are saved the LR on exception entry */</span></div><div class="line"><a name="l00721"></a><span class="lineno">  721</span>&#160;<span class="preprocessor">#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     </span><span class="comment">/* return to Handler mode, uses MSP after return                               */</span><span class="preprocessor"></span></div><div class="line"><a name="l00722"></a><span class="lineno">  722</span>&#160;<span class="preprocessor">#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     </span><span class="comment">/* return to Thread mode, uses MSP after return                                */</span><span class="preprocessor"></span></div><div class="line"><a name="l00723"></a><span class="lineno">  723</span>&#160;<span class="preprocessor">#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     </span><span class="comment">/* return to Thread mode, uses PSP after return                                */</span><span class="preprocessor"></span></div><div class="line"><a name="l00724"></a><span class="lineno">  724</span>&#160;</div><div class="line"><a name="l00725"></a><span class="lineno">  725</span>&#160;</div><div class="line"><a name="l00726"></a><span class="lineno">  726</span>&#160;<span class="comment">/* Interrupt Priorities are WORD accessible only under Armv6-M                  */</span></div><div class="line"><a name="l00727"></a><span class="lineno">  727</span>&#160;<span class="comment">/* The following MACROS handle generation of the register offset and byte masks */</span></div><div class="line"><a name="l00728"></a><span class="lineno">  728</span>&#160;<span class="preprocessor">#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &amp;  0x03UL) * 8UL)</span></div><div class="line"><a name="l00729"></a><span class="lineno">  729</span>&#160;<span class="preprocessor">#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) &amp; 0x0FUL)-8UL) &gt;&gt;    2UL)      )</span></div><div class="line"><a name="l00730"></a><span class="lineno">  730</span>&#160;<span class="preprocessor">#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                &gt;&gt;    2UL)      )</span></div><div class="line"><a name="l00731"></a><span class="lineno">  731</span>&#160;</div><div class="line"><a name="l00732"></a><span class="lineno">  732</span>&#160;<span class="preprocessor">#define __NVIC_SetPriorityGrouping(X) (void)(X)</span></div><div class="line"><a name="l00733"></a><span class="lineno">  733</span>&#160;<span class="preprocessor">#define __NVIC_GetPriorityGrouping()  (0U)</span></div><div class="line"><a name="l00734"></a><span class="lineno">  734</span>&#160;</div><div class="line"><a name="l00741"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga71227e1376cde11eda03fcb62f1b33ea">  741</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga71227e1376cde11eda03fcb62f1b33ea">__NVIC_EnableIRQ</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00742"></a><span class="lineno">  742</span>&#160;{</div><div class="line"><a name="l00743"></a><span class="lineno">  743</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00744"></a><span class="lineno">  744</span>&#160;  {</div><div class="line"><a name="l00745"></a><span class="lineno">  745</span>&#160;    <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISER[0U] = (uint32_t)(1UL &lt;&lt; (((uint32_t)IRQn) &amp; 0x1FUL));</div><div class="line"><a name="l00746"></a><span class="lineno">  746</span>&#160;  }</div><div class="line"><a name="l00747"></a><span class="lineno">  747</span>&#160;}</div><div class="line"><a name="l00748"></a><span class="lineno">  748</span>&#160;</div><div class="line"><a name="l00749"></a><span class="lineno">  749</span>&#160;</div><div class="line"><a name="l00758"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaaeb5e7cc0eaad4e2817272e7bf742083">  758</a></span>&#160;__STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaaeb5e7cc0eaad4e2817272e7bf742083">__NVIC_GetEnableIRQ</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00759"></a><span class="lineno">  759</span>&#160;{</div><div class="line"><a name="l00760"></a><span class="lineno">  760</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00761"></a><span class="lineno">  761</span>&#160;  {</div><div class="line"><a name="l00762"></a><span class="lineno">  762</span>&#160;    <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISER[0U] &amp; (1UL &lt;&lt; (((uint32_t)IRQn) &amp; 0x1FUL))) != 0UL) ? 1UL : 0UL));</div><div class="line"><a name="l00763"></a><span class="lineno">  763</span>&#160;  }</div><div class="line"><a name="l00764"></a><span class="lineno">  764</span>&#160;  <span class="keywordflow">else</span></div><div class="line"><a name="l00765"></a><span class="lineno">  765</span>&#160;  {</div><div class="line"><a name="l00766"></a><span class="lineno">  766</span>&#160;    <span class="keywordflow">return</span>(0U);</div><div class="line"><a name="l00767"></a><span class="lineno">  767</span>&#160;  }</div><div class="line"><a name="l00768"></a><span class="lineno">  768</span>&#160;}</div><div class="line"><a name="l00769"></a><span class="lineno">  769</span>&#160;</div><div class="line"><a name="l00770"></a><span class="lineno">  770</span>&#160;</div><div class="line"><a name="l00777"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gae016e4c1986312044ee768806537d52f">  777</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gae016e4c1986312044ee768806537d52f">__NVIC_DisableIRQ</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00778"></a><span class="lineno">  778</span>&#160;{</div><div class="line"><a name="l00779"></a><span class="lineno">  779</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00780"></a><span class="lineno">  780</span>&#160;  {</div><div class="line"><a name="l00781"></a><span class="lineno">  781</span>&#160;    <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ICER[0U] = (uint32_t)(1UL &lt;&lt; (((uint32_t)IRQn) &amp; 0x1FUL));</div><div class="line"><a name="l00782"></a><span class="lineno">  782</span>&#160;    <a class="code" href="group___c_m_s_i_s___core___instruction_interface.html#ga7fe277f5385d23b9c44b2cbda1577ce9">__DSB</a>();</div><div class="line"><a name="l00783"></a><span class="lineno">  783</span>&#160;    <a class="code" href="group___c_m_s_i_s___core___instruction_interface.html#gae26c2b3961e702aeabc24d4984ebd369">__ISB</a>();</div><div class="line"><a name="l00784"></a><span class="lineno">  784</span>&#160;  }</div><div class="line"><a name="l00785"></a><span class="lineno">  785</span>&#160;}</div><div class="line"><a name="l00786"></a><span class="lineno">  786</span>&#160;</div><div class="line"><a name="l00787"></a><span class="lineno">  787</span>&#160;</div><div class="line"><a name="l00796"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga5a92ca5fa801ad7adb92be7257ab9694">  796</a></span>&#160;__STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga5a92ca5fa801ad7adb92be7257ab9694">__NVIC_GetPendingIRQ</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00797"></a><span class="lineno">  797</span>&#160;{</div><div class="line"><a name="l00798"></a><span class="lineno">  798</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00799"></a><span class="lineno">  799</span>&#160;  {</div><div class="line"><a name="l00800"></a><span class="lineno">  800</span>&#160;    <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISPR[0U] &amp; (1UL &lt;&lt; (((uint32_t)IRQn) &amp; 0x1FUL))) != 0UL) ? 1UL : 0UL));</div><div class="line"><a name="l00801"></a><span class="lineno">  801</span>&#160;  }</div><div class="line"><a name="l00802"></a><span class="lineno">  802</span>&#160;  <span class="keywordflow">else</span></div><div class="line"><a name="l00803"></a><span class="lineno">  803</span>&#160;  {</div><div class="line"><a name="l00804"></a><span class="lineno">  804</span>&#160;    <span class="keywordflow">return</span>(0U);</div><div class="line"><a name="l00805"></a><span class="lineno">  805</span>&#160;  }</div><div class="line"><a name="l00806"></a><span class="lineno">  806</span>&#160;}</div><div class="line"><a name="l00807"></a><span class="lineno">  807</span>&#160;</div><div class="line"><a name="l00808"></a><span class="lineno">  808</span>&#160;</div><div class="line"><a name="l00815"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaabefdd4b790b9a7308929938c0c1e1ad">  815</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaabefdd4b790b9a7308929938c0c1e1ad">__NVIC_SetPendingIRQ</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00816"></a><span class="lineno">  816</span>&#160;{</div><div class="line"><a name="l00817"></a><span class="lineno">  817</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00818"></a><span class="lineno">  818</span>&#160;  {</div><div class="line"><a name="l00819"></a><span class="lineno">  819</span>&#160;    <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ISPR[0U] = (uint32_t)(1UL &lt;&lt; (((uint32_t)IRQn) &amp; 0x1FUL));</div><div class="line"><a name="l00820"></a><span class="lineno">  820</span>&#160;  }</div><div class="line"><a name="l00821"></a><span class="lineno">  821</span>&#160;}</div><div class="line"><a name="l00822"></a><span class="lineno">  822</span>&#160;</div><div class="line"><a name="l00823"></a><span class="lineno">  823</span>&#160;</div><div class="line"><a name="l00830"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga562a86dbdf14827d0fee8fdafb04d191">  830</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga562a86dbdf14827d0fee8fdafb04d191">__NVIC_ClearPendingIRQ</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00831"></a><span class="lineno">  831</span>&#160;{</div><div class="line"><a name="l00832"></a><span class="lineno">  832</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00833"></a><span class="lineno">  833</span>&#160;  {</div><div class="line"><a name="l00834"></a><span class="lineno">  834</span>&#160;    <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;ICPR[0U] = (uint32_t)(1UL &lt;&lt; (((uint32_t)IRQn) &amp; 0x1FUL));</div><div class="line"><a name="l00835"></a><span class="lineno">  835</span>&#160;  }</div><div class="line"><a name="l00836"></a><span class="lineno">  836</span>&#160;}</div><div class="line"><a name="l00837"></a><span class="lineno">  837</span>&#160;</div><div class="line"><a name="l00838"></a><span class="lineno">  838</span>&#160;</div><div class="line"><a name="l00848"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga505338e23563a9c074910fb14e7d45fd">  848</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga505338e23563a9c074910fb14e7d45fd">__NVIC_SetPriority</a>(IRQn_Type IRQn, uint32_t priority)</div><div class="line"><a name="l00849"></a><span class="lineno">  849</span>&#160;{</div><div class="line"><a name="l00850"></a><span class="lineno">  850</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00851"></a><span class="lineno">  851</span>&#160;  {</div><div class="line"><a name="l00852"></a><span class="lineno">  852</span>&#160;    <a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;IP[_IP_IDX(IRQn)]  = ((uint32_t)(<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;IP[_IP_IDX(IRQn)]  &amp; ~(0xFFUL &lt;&lt; _BIT_SHIFT(IRQn))) |</div><div class="line"><a name="l00853"></a><span class="lineno">  853</span>&#160;       (((priority &lt;&lt; (8U - __NVIC_PRIO_BITS)) &amp; (uint32_t)0xFFUL) &lt;&lt; _BIT_SHIFT(IRQn)));</div><div class="line"><a name="l00854"></a><span class="lineno">  854</span>&#160;  }</div><div class="line"><a name="l00855"></a><span class="lineno">  855</span>&#160;  <span class="keywordflow">else</span></div><div class="line"><a name="l00856"></a><span class="lineno">  856</span>&#160;  {</div><div class="line"><a name="l00857"></a><span class="lineno">  857</span>&#160;    <a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;SHP[_SHP_IDX(IRQn)] = ((uint32_t)(<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;SHP[_SHP_IDX(IRQn)] &amp; ~(0xFFUL &lt;&lt; _BIT_SHIFT(IRQn))) |</div><div class="line"><a name="l00858"></a><span class="lineno">  858</span>&#160;       (((priority &lt;&lt; (8U - __NVIC_PRIO_BITS)) &amp; (uint32_t)0xFFUL) &lt;&lt; _BIT_SHIFT(IRQn)));</div><div class="line"><a name="l00859"></a><span class="lineno">  859</span>&#160;  }</div><div class="line"><a name="l00860"></a><span class="lineno">  860</span>&#160;}</div><div class="line"><a name="l00861"></a><span class="lineno">  861</span>&#160;</div><div class="line"><a name="l00862"></a><span class="lineno">  862</span>&#160;</div><div class="line"><a name="l00872"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaeb9dc99c8e7700668813144261b0bc73">  872</a></span>&#160;__STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaeb9dc99c8e7700668813144261b0bc73">__NVIC_GetPriority</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00873"></a><span class="lineno">  873</span>&#160;{</div><div class="line"><a name="l00874"></a><span class="lineno">  874</span>&#160;</div><div class="line"><a name="l00875"></a><span class="lineno">  875</span>&#160;  <span class="keywordflow">if</span> ((int32_t)(IRQn) &gt;= 0)</div><div class="line"><a name="l00876"></a><span class="lineno">  876</span>&#160;  {</div><div class="line"><a name="l00877"></a><span class="lineno">  877</span>&#160;    <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a>-&gt;IP[ _IP_IDX(IRQn)] &gt;&gt; _BIT_SHIFT(IRQn) ) &amp; (uint32_t)0xFFUL) &gt;&gt; (8U - __NVIC_PRIO_BITS)));</div><div class="line"><a name="l00878"></a><span class="lineno">  878</span>&#160;  }</div><div class="line"><a name="l00879"></a><span class="lineno">  879</span>&#160;  <span class="keywordflow">else</span></div><div class="line"><a name="l00880"></a><span class="lineno">  880</span>&#160;  {</div><div class="line"><a name="l00881"></a><span class="lineno">  881</span>&#160;    <span class="keywordflow">return</span>((uint32_t)(((<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;SHP[_SHP_IDX(IRQn)] &gt;&gt; _BIT_SHIFT(IRQn) ) &amp; (uint32_t)0xFFUL) &gt;&gt; (8U - __NVIC_PRIO_BITS)));</div><div class="line"><a name="l00882"></a><span class="lineno">  882</span>&#160;  }</div><div class="line"><a name="l00883"></a><span class="lineno">  883</span>&#160;}</div><div class="line"><a name="l00884"></a><span class="lineno">  884</span>&#160;</div><div class="line"><a name="l00885"></a><span class="lineno">  885</span>&#160;</div><div class="line"><a name="l00897"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac">  897</a></span>&#160;__STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac">NVIC_EncodePriority</a> (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div><div class="line"><a name="l00898"></a><span class="lineno">  898</span>&#160;{</div><div class="line"><a name="l00899"></a><span class="lineno">  899</span>&#160;  uint32_t PriorityGroupTmp = (PriorityGroup &amp; (uint32_t)0x07UL);   <span class="comment">/* only values 0..7 are used          */</span></div><div class="line"><a name="l00900"></a><span class="lineno">  900</span>&#160;  uint32_t PreemptPriorityBits;</div><div class="line"><a name="l00901"></a><span class="lineno">  901</span>&#160;  uint32_t SubPriorityBits;</div><div class="line"><a name="l00902"></a><span class="lineno">  902</span>&#160;</div><div class="line"><a name="l00903"></a><span class="lineno">  903</span>&#160;  PreemptPriorityBits = ((7UL - PriorityGroupTmp) &gt; (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);</div><div class="line"><a name="l00904"></a><span class="lineno">  904</span>&#160;  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) &lt; (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));</div><div class="line"><a name="l00905"></a><span class="lineno">  905</span>&#160;</div><div class="line"><a name="l00906"></a><span class="lineno">  906</span>&#160;  <span class="keywordflow">return</span> (</div><div class="line"><a name="l00907"></a><span class="lineno">  907</span>&#160;           ((PreemptPriority &amp; (uint32_t)((1UL &lt;&lt; (PreemptPriorityBits)) - 1UL)) &lt;&lt; SubPriorityBits) |</div><div class="line"><a name="l00908"></a><span class="lineno">  908</span>&#160;           ((SubPriority     &amp; (uint32_t)((1UL &lt;&lt; (SubPriorityBits    )) - 1UL)))</div><div class="line"><a name="l00909"></a><span class="lineno">  909</span>&#160;         );</div><div class="line"><a name="l00910"></a><span class="lineno">  910</span>&#160;}</div><div class="line"><a name="l00911"></a><span class="lineno">  911</span>&#160;</div><div class="line"><a name="l00912"></a><span class="lineno">  912</span>&#160;</div><div class="line"><a name="l00924"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3387607fd8a1a32cccd77d2ac672dd96">  924</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3387607fd8a1a32cccd77d2ac672dd96">NVIC_DecodePriority</a> (uint32_t Priority, uint32_t PriorityGroup, uint32_t* <span class="keyword">const</span> pPreemptPriority, uint32_t* <span class="keyword">const</span> pSubPriority)</div><div class="line"><a name="l00925"></a><span class="lineno">  925</span>&#160;{</div><div class="line"><a name="l00926"></a><span class="lineno">  926</span>&#160;  uint32_t PriorityGroupTmp = (PriorityGroup &amp; (uint32_t)0x07UL);   <span class="comment">/* only values 0..7 are used          */</span></div><div class="line"><a name="l00927"></a><span class="lineno">  927</span>&#160;  uint32_t PreemptPriorityBits;</div><div class="line"><a name="l00928"></a><span class="lineno">  928</span>&#160;  uint32_t SubPriorityBits;</div><div class="line"><a name="l00929"></a><span class="lineno">  929</span>&#160;</div><div class="line"><a name="l00930"></a><span class="lineno">  930</span>&#160;  PreemptPriorityBits = ((7UL - PriorityGroupTmp) &gt; (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);</div><div class="line"><a name="l00931"></a><span class="lineno">  931</span>&#160;  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) &lt; (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));</div><div class="line"><a name="l00932"></a><span class="lineno">  932</span>&#160;</div><div class="line"><a name="l00933"></a><span class="lineno">  933</span>&#160;  *pPreemptPriority = (Priority &gt;&gt; SubPriorityBits) &amp; (uint32_t)((1UL &lt;&lt; (PreemptPriorityBits)) - 1UL);</div><div class="line"><a name="l00934"></a><span class="lineno">  934</span>&#160;  *pSubPriority     = (Priority                   ) &amp; (uint32_t)((1UL &lt;&lt; (SubPriorityBits    )) - 1UL);</div><div class="line"><a name="l00935"></a><span class="lineno">  935</span>&#160;}</div><div class="line"><a name="l00936"></a><span class="lineno">  936</span>&#160;</div><div class="line"><a name="l00937"></a><span class="lineno">  937</span>&#160;</div><div class="line"><a name="l00948"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0df355460bc1783d58f9d72ee4884208">  948</a></span>&#160;__STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0df355460bc1783d58f9d72ee4884208">__NVIC_SetVector</a>(IRQn_Type IRQn, uint32_t vector)</div><div class="line"><a name="l00949"></a><span class="lineno">  949</span>&#160;{</div><div class="line"><a name="l00950"></a><span class="lineno">  950</span>&#160;<span class="preprocessor">#if defined (__VTOR_PRESENT) &amp;&amp; (__VTOR_PRESENT == 1U)</span></div><div class="line"><a name="l00951"></a><span class="lineno">  951</span>&#160;  uint32_t *vectors = (uint32_t *)<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;VTOR;</div><div class="line"><a name="l00952"></a><span class="lineno">  952</span>&#160;#<span class="keywordflow">else</span></div><div class="line"><a name="l00953"></a><span class="lineno">  953</span>&#160;    uint32_t *vectors = (uint32_t *)0x0U;</div><div class="line"><a name="l00954"></a><span class="lineno">  954</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00955"></a><span class="lineno">  955</span>&#160;  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;</div><div class="line"><a name="l00956"></a><span class="lineno">  956</span>&#160;}</div><div class="line"><a name="l00957"></a><span class="lineno">  957</span>&#160;</div><div class="line"><a name="l00958"></a><span class="lineno">  958</span>&#160;</div><div class="line"><a name="l00967"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga44b665d2afb708121d9b10c76ff00ee5">  967</a></span>&#160;__STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga44b665d2afb708121d9b10c76ff00ee5">__NVIC_GetVector</a>(IRQn_Type IRQn)</div><div class="line"><a name="l00968"></a><span class="lineno">  968</span>&#160;{</div><div class="line"><a name="l00969"></a><span class="lineno">  969</span>&#160;<span class="preprocessor">#if defined (__VTOR_PRESENT) &amp;&amp; (__VTOR_PRESENT == 1U)</span></div><div class="line"><a name="l00970"></a><span class="lineno">  970</span>&#160;  uint32_t *vectors = (uint32_t *)<a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;VTOR;</div><div class="line"><a name="l00971"></a><span class="lineno">  971</span>&#160;#<span class="keywordflow">else</span></div><div class="line"><a name="l00972"></a><span class="lineno">  972</span>&#160;  uint32_t *vectors = (uint32_t *)0x0U;</div><div class="line"><a name="l00973"></a><span class="lineno">  973</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00974"></a><span class="lineno">  974</span>&#160;  <span class="keywordflow">return</span> vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];</div><div class="line"><a name="l00975"></a><span class="lineno">  975</span>&#160;</div><div class="line"><a name="l00976"></a><span class="lineno">  976</span>&#160;}</div><div class="line"><a name="l00977"></a><span class="lineno">  977</span>&#160;</div><div class="line"><a name="l00978"></a><span class="lineno">  978</span>&#160;</div><div class="line"><a name="l00983"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0d9aa2d30fa54b41eb780c16e35b676c">  983</a></span>&#160;__NO_RETURN __STATIC_INLINE <span class="keywordtype">void</span> <a class="code" href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0d9aa2d30fa54b41eb780c16e35b676c">__NVIC_SystemReset</a>(<span class="keywordtype">void</span>)</div><div class="line"><a name="l00984"></a><span class="lineno">  984</span>&#160;{</div><div class="line"><a name="l00985"></a><span class="lineno">  985</span>&#160;  <a class="code" href="group___c_m_s_i_s___core___instruction_interface.html#ga7fe277f5385d23b9c44b2cbda1577ce9">__DSB</a>();                                                          <span class="comment">/* Ensure all outstanding memory accesses included</span></div><div class="line"><a name="l00986"></a><span class="lineno">  986</span>&#160;<span class="comment">                                                                       buffered write are completed before reset */</span></div><div class="line"><a name="l00987"></a><span class="lineno">  987</span>&#160;  <a class="code" href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a>-&gt;AIRCR  = ((0x5FAUL &lt;&lt; <a class="code" href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a>) |</div><div class="line"><a name="l00988"></a><span class="lineno">  988</span>&#160;                 <a class="code" href="group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a>);</div><div class="line"><a name="l00989"></a><span class="lineno">  989</span>&#160;  <a class="code" href="group___c_m_s_i_s___core___instruction_interface.html#ga7fe277f5385d23b9c44b2cbda1577ce9">__DSB</a>();                                                          <span class="comment">/* Ensure completion of memory access */</span></div><div class="line"><a name="l00990"></a><span class="lineno">  990</span>&#160;</div><div class="line"><a name="l00991"></a><span class="lineno">  991</span>&#160;  <span class="keywordflow">for</span>(;;)                                                           <span class="comment">/* wait until reset */</span></div><div class="line"><a name="l00992"></a><span class="lineno">  992</span>&#160;  {</div><div class="line"><a name="l00993"></a><span class="lineno">  993</span>&#160;    <a class="code" href="group___c_m_s_i_s___core___instruction_interface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a>();</div><div class="line"><a name="l00994"></a><span class="lineno">  994</span>&#160;  }</div><div class="line"><a name="l00995"></a><span class="lineno">  995</span>&#160;}</div><div class="line"><a name="l00996"></a><span class="lineno">  996</span>&#160;</div><div class="line"><a name="l00999"></a><span class="lineno">  999</span>&#160;<span class="comment">/* ##########################  MPU functions  #################################### */</span></div><div class="line"><a name="l01000"></a><span class="lineno"> 1000</span>&#160;</div><div class="line"><a name="l01001"></a><span class="lineno"> 1001</span>&#160;<span class="preprocessor">#if defined (__MPU_PRESENT) &amp;&amp; (__MPU_PRESENT == 1U)</span></div><div class="line"><a name="l01002"></a><span class="lineno"> 1002</span>&#160;</div><div class="line"><a name="l01003"></a><span class="lineno"> 1003</span>&#160;<span class="preprocessor">#include &quot;mpu_armv7.h&quot;</span></div><div class="line"><a name="l01004"></a><span class="lineno"> 1004</span>&#160;</div><div class="line"><a name="l01005"></a><span class="lineno"> 1005</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l01006"></a><span class="lineno"> 1006</span>&#160;</div><div class="line"><a name="l01007"></a><span class="lineno"> 1007</span>&#160;<span class="comment">/* ##########################  FPU functions  #################################### */</span></div><div class="line"><a name="l01023"></a><span class="lineno"><a class="line" href="group___c_m_s_i_s___core___fpu_functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756"> 1023</a></span>&#160;__STATIC_INLINE uint32_t <a class="code" href="group___c_m_s_i_s___core___fpu_functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>(<span class="keywordtype">void</span>)</div><div class="line"><a name="l01024"></a><span class="lineno"> 1024</span>&#160;{</div><div class="line"><a name="l01025"></a><span class="lineno"> 1025</span>&#160;    <span class="keywordflow">return</span> 0U;           <span class="comment">/* No FPU */</span></div><div class="line"><a name="l01026"></a><span class="lineno"> 1026</span>&#160;}</div><div class="line"><a name="l01027"></a><span class="lineno"> 1027</span>&#160;</div><div class="line"><a name="l01028"></a><span class="lineno"> 1028</span>&#160;</div><div class="line"><a name="l01033"></a><span class="lineno"> 1033</span>&#160;<span class="comment">/* ##################################    SysTick function  ############################################ */</span></div><div class="line"><a name="l01041"></a><span class="lineno"> 1041</span>&#160;<span class="preprocessor">#if defined (__Vendor_SysTickConfig) &amp;&amp; (__Vendor_SysTickConfig == 0U)</span></div><div class="line"><a name="l01042"></a><span class="lineno"> 1042</span>&#160;</div><div class="line"><a name="l01054"></a><span class="lineno"> 1054</span>&#160;__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)</div><div class="line"><a name="l01055"></a><span class="lineno"> 1055</span>&#160;{</div><div class="line"><a name="l01056"></a><span class="lineno"> 1056</span>&#160;  <span class="keywordflow">if</span> ((ticks - 1UL) &gt; <a class="code" href="group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a>)</div><div class="line"><a name="l01057"></a><span class="lineno"> 1057</span>&#160;  {</div><div class="line"><a name="l01058"></a><span class="lineno"> 1058</span>&#160;    <span class="keywordflow">return</span> (1UL);                                                   <span class="comment">/* Reload value impossible */</span></div><div class="line"><a name="l01059"></a><span class="lineno"> 1059</span>&#160;  }</div><div class="line"><a name="l01060"></a><span class="lineno"> 1060</span>&#160;</div><div class="line"><a name="l01061"></a><span class="lineno"> 1061</span>&#160;  <a class="code" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>-&gt;LOAD  = (uint32_t)(ticks - 1UL);                         <span class="comment">/* set reload register */</span></div><div class="line"><a name="l01062"></a><span class="lineno"> 1062</span>&#160;  NVIC_SetPriority (SysTick_IRQn, (1UL &lt;&lt; __NVIC_PRIO_BITS) - 1UL); <span class="comment">/* set Priority for Systick Interrupt */</span></div><div class="line"><a name="l01063"></a><span class="lineno"> 1063</span>&#160;  <a class="code" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>-&gt;VAL   = 0UL;                                             <span class="comment">/* Load the SysTick Counter Value */</span></div><div class="line"><a name="l01064"></a><span class="lineno"> 1064</span>&#160;  <a class="code" href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a>-&gt;CTRL  = <a class="code" href="group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a> |</div><div class="line"><a name="l01065"></a><span class="lineno"> 1065</span>&#160;                   <a class="code" href="group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a>   |</div><div class="line"><a name="l01066"></a><span class="lineno"> 1066</span>&#160;                   <a class="code" href="group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a>;                         <span class="comment">/* Enable SysTick IRQ and SysTick Timer */</span></div><div class="line"><a name="l01067"></a><span class="lineno"> 1067</span>&#160;  <span class="keywordflow">return</span> (0UL);                                                     <span class="comment">/* Function successful */</span></div><div class="line"><a name="l01068"></a><span class="lineno"> 1068</span>&#160;}</div><div class="line"><a name="l01069"></a><span class="lineno"> 1069</span>&#160;</div><div class="line"><a name="l01070"></a><span class="lineno"> 1070</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l01071"></a><span class="lineno"> 1071</span>&#160;</div><div class="line"><a name="l01077"></a><span class="lineno"> 1077</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l01078"></a><span class="lineno"> 1078</span>&#160;}</div><div class="line"><a name="l01079"></a><span class="lineno"> 1079</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l01080"></a><span class="lineno"> 1080</span>&#160;</div><div class="line"><a name="l01081"></a><span class="lineno"> 1081</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* __CORE_CM0PLUS_H_DEPENDANT */</span><span class="preprocessor"></span></div><div class="line"><a name="l01082"></a><span class="lineno"> 1082</span>&#160;</div><div class="line"><a name="l01083"></a><span class="lineno"> 1083</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* __CMSIS_GENERIC */</span><span class="preprocessor"></span></div><div class="ttc" id="group___c_m_s_i_s___core___instruction_interface_html_gabd585ddc865fb9b7f2493af1eee1a572"><div class="ttname"><a href="group___c_m_s_i_s___core___instruction_interface.html#gabd585ddc865fb9b7f2493af1eee1a572">__NOP</a></div><div class="ttdeci">#define __NOP</div><div class="ttdoc">No Operation.</div><div class="ttdef"><b>Definition:</b> cmsis_armcc.h:387</div></div>
<div class="ttc" id="union_c_o_n_t_r_o_l___type_html_a2a6e513e8a6bf4e58db169e312172332"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html#a2a6e513e8a6bf4e58db169e312172332">CONTROL_Type::nPRIV</a></div><div class="ttdeci">uint32_t nPRIV</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:301</div></div>
<div class="ttc" id="union_c_o_n_t_r_o_l___type_html_ae185aac93686ffc78e998a9daf41415b"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html#ae185aac93686ffc78e998a9daf41415b">CONTROL_Type::SPSEL</a></div><div class="ttdeci">uint32_t SPSEL</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:302</div></div>
<div class="ttc" id="union_c_o_n_t_r_o_l___type_html_a959a73d8faee56599b7e792a7c5a2d16"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html#a959a73d8faee56599b7e792a7c5a2d16">CONTROL_Type::_reserved1</a></div><div class="ttdeci">uint32_t _reserved1</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:303</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gaaeb5e7cc0eaad4e2817272e7bf742083"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaaeb5e7cc0eaad4e2817272e7bf742083">__NVIC_GetEnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Enable status.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:758</div></div>
<div class="ttc" id="group___c_m_s_i_s__core__base_html_gacd96c53beeaff8f603fcda425eb295de"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gacd96c53beeaff8f603fcda425eb295de">SysTick</a></div><div class="ttdeci">#define SysTick</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:654</div></div>
<div class="ttc" id="union_a_p_s_r___type_html_a5ae954cbd9986cd64625d7fa00943c8e"><div class="ttname"><a href="union_a_p_s_r___type.html#a5ae954cbd9986cd64625d7fa00943c8e">APSR_Type::Z</a></div><div class="ttdeci">uint32_t Z</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:217</div></div>
<div class="ttc" id="union_i_p_s_r___type_html_ad0fb62e7a08e70fc5e0a76b67809f84b"><div class="ttname"><a href="union_i_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">IPSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:247</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga44b665d2afb708121d9b10c76ff00ee5"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga44b665d2afb708121d9b10c76ff00ee5">__NVIC_GetVector</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Vector.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:967</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_a959a73d8faee56599b7e792a7c5a2d16"><div class="ttname"><a href="unionx_p_s_r___type.html#a959a73d8faee56599b7e792a7c5a2d16">xPSR_Type::_reserved1</a></div><div class="ttdeci">uint32_t _reserved1</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:265</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga71227e1376cde11eda03fcb62f1b33ea"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga71227e1376cde11eda03fcb62f1b33ea">__NVIC_EnableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Enable Interrupt.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:741</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga5a92ca5fa801ad7adb92be7257ab9694"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga5a92ca5fa801ad7adb92be7257ab9694">__NVIC_GetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Get Pending Interrupt.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:796</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gaabefdd4b790b9a7308929938c0c1e1ad"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaabefdd4b790b9a7308929938c0c1e1ad">__NVIC_SetPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Set Pending Interrupt.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:815</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_ad502ba7dbb2aab5f87c782b28f02622d"><div class="ttname"><a href="unionx_p_s_r___type.html#ad502ba7dbb2aab5f87c782b28f02622d">xPSR_Type::ISR</a></div><div class="ttdeci">uint32_t ISR</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:262</div></div>
<div class="ttc" id="union_i_p_s_r___type_html"><div class="ttname"><a href="union_i_p_s_r___type.html">IPSR_Type</a></div><div class="ttdoc">Union type to access the Interrupt Program Status Register (IPSR).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:240</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_ad0fb62e7a08e70fc5e0a76b67809f84b"><div class="ttname"><a href="unionx_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">xPSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:271</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___fpu_functions_html_ga6bcad99ce80a0e7e4ddc6f2379081756"><div class="ttname"><a href="group___c_m_s_i_s___core___fpu_functions.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a></div><div class="ttdeci">__STATIC_INLINE uint32_t SCB_GetFPUType(void)</div><div class="ttdoc">get FPU type</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:1023</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga3387607fd8a1a32cccd77d2ac672dd96"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga3387607fd8a1a32cccd77d2ac672dd96">NVIC_DecodePriority</a></div><div class="ttdeci">__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)</div><div class="ttdoc">Decode Priority.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:924</div></div>
<div class="ttc" id="group___c_m_s_i_s__core__base_html_gac8e97e8ce56ae9f57da1363a937f8a17"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gac8e97e8ce56ae9f57da1363a937f8a17">NVIC</a></div><div class="ttdeci">#define NVIC</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:655</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___instruction_interface_html_ga7fe277f5385d23b9c44b2cbda1577ce9"><div class="ttname"><a href="group___c_m_s_i_s___core___instruction_interface.html#ga7fe277f5385d23b9c44b2cbda1577ce9">__DSB</a></div><div class="ttdeci">__STATIC_FORCEINLINE void __DSB(void)</div><div class="ttdoc">Data Synchronization Barrier.</div><div class="ttdef"><b>Definition:</b> cmsis_gcc.h:877</div></div>
<div class="ttc" id="cmsis__version_8h_html"><div class="ttname"><a href="cmsis__version_8h.html">cmsis_version.h</a></div><div class="ttdoc">CMSIS Core(M) Version definitions.</div></div>
<div class="ttc" id="struct_s_c_b___type_html"><div class="ttname"><a href="struct_s_c_b___type.html">SCB_Type</a></div><div class="ttdoc">Structure type to access the System Control Block (SCB).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:355</div></div>
<div class="ttc" id="group___c_m_s_i_s__core__base_html_gaaaf6477c2bde2f00f99e3c2fd1060b01"><div class="ttname"><a href="group___c_m_s_i_s__core__base.html#gaaaf6477c2bde2f00f99e3c2fd1060b01">SCB</a></div><div class="ttdeci">#define SCB</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:653</div></div>
<div class="ttc" id="union_a_p_s_r___type_html_abae0610bc2a97bbf7f689e953e0b451f"><div class="ttname"><a href="union_a_p_s_r___type.html#abae0610bc2a97bbf7f689e953e0b451f">APSR_Type::N</a></div><div class="ttdeci">uint32_t N</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:218</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_a7a1caf92f32fe9ebd8d1fe89b06c7776"><div class="ttname"><a href="unionx_p_s_r___type.html#a7a1caf92f32fe9ebd8d1fe89b06c7776">xPSR_Type::C</a></div><div class="ttdeci">uint32_t C</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:267</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga0df355460bc1783d58f9d72ee4884208"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0df355460bc1783d58f9d72ee4884208">__NVIC_SetVector</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)</div><div class="ttdoc">Set Interrupt Vector.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:948</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gae016e4c1986312044ee768806537d52f"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gae016e4c1986312044ee768806537d52f">__NVIC_DisableIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Disable Interrupt.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:777</div></div>
<div class="ttc" id="union_a_p_s_r___type_html_ac8a6a13838a897c8d0b8bc991bbaf7c1"><div class="ttname"><a href="union_a_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">APSR_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:214</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_ac8a6a13838a897c8d0b8bc991bbaf7c1"><div class="ttname"><a href="unionx_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">xPSR_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:263</div></div>
<div class="ttc" id="struct_n_v_i_c___type_html"><div class="ttname"><a href="struct_n_v_i_c___type.html">NVIC_Type</a></div><div class="ttdoc">Structure type to access the Nested Vectored Interrupt Controller (NVIC).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:328</div></div>
<div class="ttc" id="struct_sys_tick___type_html"><div class="ttname"><a href="struct_sys_tick___type.html">SysTick_Type</a></div><div class="ttdoc">Structure type to access the System Timer (SysTick).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:472</div></div>
<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_gaaa27c0ba600bf82c3da08c748845b640"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#gaaa27c0ba600bf82c3da08c748845b640">SCB_AIRCR_VECTKEY_Pos</a></div><div class="ttdeci">#define SCB_AIRCR_VECTKEY_Pos</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:423</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_a6e1cf12e53a20224f6f62c001d9be972"><div class="ttname"><a href="unionx_p_s_r___type.html#a6e1cf12e53a20224f6f62c001d9be972">xPSR_Type::T</a></div><div class="ttdeci">uint32_t T</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:264</div></div>
<div class="ttc" id="union_a_p_s_r___type_html_ad0fb62e7a08e70fc5e0a76b67809f84b"><div class="ttname"><a href="union_a_p_s_r___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">APSR_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:220</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga505338e23563a9c074910fb14e7d45fd"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga505338e23563a9c074910fb14e7d45fd">__NVIC_SetPriority</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set Interrupt Priority.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:848</div></div>
<div class="ttc" id="union_a_p_s_r___type_html_a7a1caf92f32fe9ebd8d1fe89b06c7776"><div class="ttname"><a href="union_a_p_s_r___type.html#a7a1caf92f32fe9ebd8d1fe89b06c7776">APSR_Type::C</a></div><div class="ttdeci">uint32_t C</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:216</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_abae0610bc2a97bbf7f689e953e0b451f"><div class="ttname"><a href="unionx_p_s_r___type.html#abae0610bc2a97bbf7f689e953e0b451f">xPSR_Type::N</a></div><div class="ttdeci">uint32_t N</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:269</div></div>
<div class="ttc" id="group___c_m_s_i_s___s_c_b_html_gaae1181119559a5bd36e62afa373fa720"><div class="ttname"><a href="group___c_m_s_i_s___s_c_b.html#gaae1181119559a5bd36e62afa373fa720">SCB_AIRCR_SYSRESETREQ_Msk</a></div><div class="ttdeci">#define SCB_AIRCR_SYSRESETREQ_Msk</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:433</div></div>
<div class="ttc" id="cmsis__compiler_8h_html"><div class="ttname"><a href="cmsis__compiler_8h.html">cmsis_compiler.h</a></div><div class="ttdoc">CMSIS compiler generic header file.</div></div>
<div class="ttc" id="union_a_p_s_r___type_html"><div class="ttname"><a href="union_a_p_s_r___type.html">APSR_Type</a></div><div class="ttdoc">Union type to access the Application Program Status Register (APSR).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:210</div></div>
<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_ga265912a7962f0e1abd170336e579b1b1"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#ga265912a7962f0e1abd170336e579b1b1">SysTick_LOAD_RELOAD_Msk</a></div><div class="ttdeci">#define SysTick_LOAD_RELOAD_Msk</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:495</div></div>
<div class="ttc" id="union_i_p_s_r___type_html_ad502ba7dbb2aab5f87c782b28f02622d"><div class="ttname"><a href="union_i_p_s_r___type.html#ad502ba7dbb2aab5f87c782b28f02622d">IPSR_Type::ISR</a></div><div class="ttdeci">uint32_t ISR</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:244</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga562a86dbdf14827d0fee8fdafb04d191"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga562a86dbdf14827d0fee8fdafb04d191">__NVIC_ClearPendingIRQ</a></div><div class="ttdeci">__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)</div><div class="ttdoc">Clear Pending Interrupt.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:830</div></div>
<div class="ttc" id="union_c_o_n_t_r_o_l___type_html"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a></div><div class="ttdoc">Union type to access the Control Registers (CONTROL).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:297</div></div>
<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_gaa41d06039797423a46596bd313d57373"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#gaa41d06039797423a46596bd313d57373">SysTick_CTRL_CLKSOURCE_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_CLKSOURCE_Msk</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:485</div></div>
<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_ga16c9fee0ed0235524bdeb38af328fd1f"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#ga16c9fee0ed0235524bdeb38af328fd1f">SysTick_CTRL_ENABLE_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_ENABLE_Msk</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:491</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_acd4a2b64faee91e4a9eef300667fa222"><div class="ttname"><a href="unionx_p_s_r___type.html#acd4a2b64faee91e4a9eef300667fa222">xPSR_Type::V</a></div><div class="ttdeci">uint32_t V</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:266</div></div>
<div class="ttc" id="union_a_p_s_r___type_html_acd4a2b64faee91e4a9eef300667fa222"><div class="ttname"><a href="union_a_p_s_r___type.html#acd4a2b64faee91e4a9eef300667fa222">APSR_Type::V</a></div><div class="ttdeci">uint32_t V</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:215</div></div>
<div class="ttc" id="union_c_o_n_t_r_o_l___type_html_ad0fb62e7a08e70fc5e0a76b67809f84b"><div class="ttname"><a href="union_c_o_n_t_r_o_l___type.html#ad0fb62e7a08e70fc5e0a76b67809f84b">CONTROL_Type::w</a></div><div class="ttdeci">uint32_t w</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:305</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gadb94ac5d892b376e4f3555ae0418ebac"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gadb94ac5d892b376e4f3555ae0418ebac">NVIC_EncodePriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</div><div class="ttdoc">Encode Priority.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:897</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_ga0d9aa2d30fa54b41eb780c16e35b676c"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#ga0d9aa2d30fa54b41eb780c16e35b676c">__NVIC_SystemReset</a></div><div class="ttdeci">__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)</div><div class="ttdoc">System Reset.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:983</div></div>
<div class="ttc" id="unionx_p_s_r___type_html"><div class="ttname"><a href="unionx_p_s_r___type.html">xPSR_Type</a></div><div class="ttdoc">Union type to access the Special-Purpose Program Status Registers (xPSR).</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:258</div></div>
<div class="ttc" id="unionx_p_s_r___type_html_a5ae954cbd9986cd64625d7fa00943c8e"><div class="ttname"><a href="unionx_p_s_r___type.html#a5ae954cbd9986cd64625d7fa00943c8e">xPSR_Type::Z</a></div><div class="ttdeci">uint32_t Z</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:268</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___instruction_interface_html_gae26c2b3961e702aeabc24d4984ebd369"><div class="ttname"><a href="group___c_m_s_i_s___core___instruction_interface.html#gae26c2b3961e702aeabc24d4984ebd369">__ISB</a></div><div class="ttdeci">__STATIC_FORCEINLINE void __ISB(void)</div><div class="ttdoc">Instruction Synchronization Barrier.</div><div class="ttdef"><b>Definition:</b> cmsis_gcc.h:866</div></div>
<div class="ttc" id="group___c_m_s_i_s___core___n_v_i_c_functions_html_gaeb9dc99c8e7700668813144261b0bc73"><div class="ttname"><a href="group___c_m_s_i_s___core___n_v_i_c_functions.html#gaeb9dc99c8e7700668813144261b0bc73">__NVIC_GetPriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Get Interrupt Priority.</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:872</div></div>
<div class="ttc" id="union_i_p_s_r___type_html_ac8a6a13838a897c8d0b8bc991bbaf7c1"><div class="ttname"><a href="union_i_p_s_r___type.html#ac8a6a13838a897c8d0b8bc991bbaf7c1">IPSR_Type::_reserved0</a></div><div class="ttdeci">uint32_t _reserved0</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:245</div></div>
<div class="ttc" id="group___c_m_s_i_s___sys_tick_html_ga95bb984266ca764024836a870238a027"><div class="ttname"><a href="group___c_m_s_i_s___sys_tick.html#ga95bb984266ca764024836a870238a027">SysTick_CTRL_TICKINT_Msk</a></div><div class="ttdeci">#define SysTick_CTRL_TICKINT_Msk</div><div class="ttdef"><b>Definition:</b> core_cm0plus.h:488</div></div>
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